As integrated circuits become more and more complex, it becomes more difficult to test the various circuits on an integrated circuit. Built-in-self-test (BIST) scan testing is a common testing methodology, well-known in the art, which can be used to test the various circuits on an integrated circuit. Unfortunately, however, BIST scan testing generally requires a significant amount of circuitry which must be added to the integrated circuit merely for purposes of testing.
For example, most BIST scan testing techniques require circuitry for generating a plurality of pseudo-random bits which are used as scan input bits to the circuits under test. Most BIST scan testing techniques also require circuitry for performing data compression on the long stream of scan output bits produced by the circuits under test. The output of the data compression step, the actual result, is then compared to the expected result. If the actual result is different than the expected result, the integrated circuit has failed the test. If the actual result is the same as the expected result, the integrated circuit has passed the test.
A linear-feedback shift-register (LFSR) is commonly used to generate pseudo-random numbers. An LFSR is a multi-stage shift-register with feedback connections via exclusive-OR (XOR) gates. Outputs of the last stage and some intermediate stages are tapped and fed back to the first stage via XOR-gates. The first and last stages being the leftmost and rightmost bit-positions, respectively, if the register shifts left-to-right. In existing LFSRs, the polynomial which is used to generate the pseudo-random numbers is determined by the hardwired feedback connections from the various stages of the LFSR. Note that a shift register which shifts right-to-left may alternately be used. Also, there are a variety of possible implementations of LFSRs, such as type 1 and type 2. The use of an LFSR for generating pseudo-random numbers is well-known in the art.
A multiple input signature register (MISR) is often used to perform data compression. Like the LFSR, the MISR is a multi-stage shift-register with feedback connections via exclusive-OR (XOR) gates. Outputs of the last stage and some intermediate stages are tapped and fed back to the first stage via XOR-gates. The first and last stages being the leftmost and rightmost bit-positions, respectively, if the register shifts left-to-right. In existing MISRs, the polynomial which is used for data compression is determined by the hardwired feedback connections from the various stages of the MISR. Note that a shift register which shifts right-to-left may alternately be used. Also, there are a variety of possible implementations of MISRs, such as type 1 and type 2. The use of a MISR for performing data compression is well-known in the art.
Many integrated circuits today incorporate some form of self-test capability. The MC68HC11 family of microcontrollers, (available from Motorola, Inc. of Austin, Tex.) uses a bootstrap mode which can be used in conjunction with a serial communication interface to perform a self-test. The MC68HC11 bootstrap mode uses self-test software which is loaded into the on-board random access memory (RAM) by means of the serial communication interface. The MC68HC11 family of microcontrollers does not use BIST scan testing. The Intel 80486 microprocessor (available from Intel, Corp. of Santa Clara, Calif.) has a built-in-self-test capability and a scan test capability which requires a significant amount of dedicated circuitry.
Self-test capability is quickly becoming a necessary feature of many integrated circuits. However some self-test techniques, such as BIST scan testing, require a significant amount of specialized test circuitry in order to sufficiently test an integrated circuit. The addition of this specialized test circuitry increases the integrated circuit die size, and thus increases the cost of the integrated circuit.